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The PDP-11 was a 16-bit minicomputer sold by Digital Equipment Corp in the 1970s and 1980s. The PDP-11 was a successor to DEC's PDP-8 computer in the PDP series of computers. It has several uniquely innovative features, and its simple but effective design, felt by many to be the best 16-bit instruction set ever, led to it becoming one of the most influental, and imitated, computers in history.

The success of the PDP-11 inspired the design of a number of similar successful CPU architectures, such as DEC's own successor to the PDP-11, the VAX supermini, as well as the Motorola 68000 microprocessor family.

Table of contents
1 Important Ideas
2 The LSI-11
3 Architectural Details
4 Assembly Language Programming Example
5 Operating Systems
6 PDP-11 Clones
7 External links

Important Ideas

First, the instruction set was one of the most orthogonal ever designed. This means that each operation, i.e. addition, subtraction, etc., was cleanly and precisely separated from the method to locate the operands. This property is called "orthogonality" in an allusion to linear mathematics. This made the computer much easier to program because a programmer could memorize the operations, and the methods of accessing operands. He could then predict that any access method (or, "addressing mode") would work with any operation. He did not have to learn a list of exceptions or special cases in which an operation had a special or restricted set of addressing modes. In some logical sense, the set of addressing modes provided one "basis" and the set of operations provided another. Each is instruction separated into two six-bit address modes and a four-bit op-code. All op-codes operated with any combination of address modes. There were 8 general-purpose registers numbered 0 through 7. Any register could be used for most purposes, although register 6 was elected as the stack pointer for subroutines, and register 7 was used as program counter.

In the most radical departure from other, earlier computers, the PDP-11 had no dedicated bus for input/output; it had only a memory bus. All input and output devices were mapped to addresses in memory, so in addition, no special I/O instructions were needed.. The interrupt system was intentionally designed to be as simple as possible, while assuring that no event in an interrupt sequence could be missed. A device would request an interrupt by asserting an input into an interrupt daisy chain. A daisy chain is a sequence of logic gates arranged in series to prioritize events. Generally the first logic gate is for the highest priority. The daisy chain order established the priority of the device. In the case of the PDP-11 design, this meant that the interrupt priority order was determined by how close the physical hardware was to the CPU. When the CPU responded, the device would place its vector (interrupt number) on the bus. The CPU would then load the status register and starting address from the vector table, and temporarily disable interrupts. The CPU would multiply the vector by a power of two (usually just 2), and then fetch a number from that address. The address would be the starting address of code to run for the interrupt. The interrupt code would then service the device, and in the process, write to the interrupting device to turn off the interrupt signal. Finally, a special RTI (return from interrupt) instruction would enable interrupts on all devices. Note that this process prevents loss of interrupts. At every stage, if the interrupt is not serviced, it remains in place, to be sensed on the next cycle. If a sequence is erroneously started, the CPU would time out, generating a spurious interrupt. The spurious interrupt would warn users of bad hardware.

Finally , the PDP-11 was designed to be produced in a factory by semiskilled labor. All of the dimensions of its pieces were relatively noncritical. All parts of the computer chassis were constructed from injection-molded plastic, or bent steel rod (lighter than sheet metal). It used a push-bonded backplane. That is, the printed circuit board plugged into a backplane connector. The backplane connector had terminals that could be connected by pushing wires into them. The terminal would cut the insulation around the wire and bite into the wire to for a gas-tight (i.e. corrosion-proof, therefore reliable) connection. The connector blocks were very similar to telephone connection blocks. The case was injection-molded plastic that snapped over the steel-rod chassis.

The LSI-11

The LSI-11 was the first PDP-11 model produced using large-scale integration; the entire CPU was contained on 4 LSI chips. It used a variant of the Unibus backplane called the Q-Bus.

The CPU's microcode included a debugger that directly communicated to a standard RS-232 terminal. This was innovative because the microcode is the part of the irreducible guts of the computer, a critical part of the control unit. If it doesn't work, there is no computer. The debugger provided a way to examine the computer's registers, memory and input and output devices. Thus, if the CPU worked at all, it was possible to examine and correct the computer's internal state. The built-in debugger avoided the expense and inconvenience of a front panel with an array of switches and lights, which was then the typical way to enter digital data into a near-dead computer.

The microcode also included a generic bootstrap, to which all DEC disk drives were compatible.

These two innovations meant that most of the time, the computer just worked. If it did not boot from its big disk, it would boot from its floppy. If the hardware worked at all, it talked to you through a terminal in a familiar way.

Architectural Details

The following information is found in DEC's PDP-11 Processor Handbook (see Gordon Bell's 1969 edition).

General register addressing modes

(R is a general register, 0 to 7; (R) is the contents of that register.)
0. Register - the value is to or from a register: OPR R ; R contains operand
1. Register deferred - register is used as a memory address to read or write: OPR (R) ; R contains address
2. Autoincrement: OPR (R)+ ; R contains address, then increment (R)
3. Autoincrement deferred: OPR @(R)+ ; R contains address of address, then increment (R) by 2
4. Autodecrement: OPR -(R) ; Decrement (R), then R contains address
5. Autodecrement deferred: OPR @-(R) ; Decrement (R) by 2, then R contains address of address
6. Index: OPR X(R) ; (R)+X is address, second word of instruction
7. Index deferred: OPR @X(R) ; (R)+X is address (second word) of address

Program Counter addressing modes

The program counter (PC) can also be used as a general purpose register, providing the following additional modes:
2. Immediate: OPR #N ; Operand is contained in the instruction
3. Absolute: OPR @#A ; Absolute address is contained in the instruction
6. Relative: OPR A ; PC+4+X is address. PC+4 is updated PC
7. Relative deferred: OPR @A ; PC+4+X is address of address. PC+4 is updated PC

PDP-11 instructions

The four condition codes in the processor status word (PSW) are

Assembly Language Programming Example

A complete "
Hello, world" program in PDP-11 macro assembler, to run under RT-11:
        BEQ     DONE    ;IF ZERO, EXIT LOOP
        BR      1$      ;REPEAT LOOP


(Exercise for the reader: how can the above code be improved to avoid one of the branch instructions in the inner loop?)

If this file is HELLO.MAC, the RT-11 commands to assemble, link and run (with console output shown) are as follows:




(The RT-11 command prompt is ".")

For a more complicated example of MACRO-11 code, see Kevin Murrell's KPUN.MAC.

You try out the above for yourself on a PDP-11 emulator. Bob Supnik's outstanding simh emulates the PDP-11 and a variety of other architectures, and includes software kits for native operating systems (including RT-11).

Operating Systems

Several operating systems were available for the PDP-11

PDP-11 Clones

Several clones were also produced including:

External links