A Complex Instruction Set Computer (CISC) is an instruction set architecture (ISA) in which each instruction can indicate several low-level operations, such as a load from memory, an arithmetic operations, and a memory store, all in a single instruction. The term was coined in contrast to Reduced Instruction Set Computer (RISC).
Before the first RISC processors were designed, many computer architects tried to bridge the "semantic gap" - to design instruction sets to support high-level languages by providing "high-level" instructions such as procedure call and return, loop instructions such as "decrement and branch if non-zero" and complex addressing modes to allow data structure and array accesses to be combined into single instructions. Additionally, the compact nature of a CISC ISA results in smaller program sizes and fewer calls to main memory, which at the time (the 1960s) resulted in a tremendous savings on the cost of a computer.
While these architectures achieved their aim of allowing high-level language constructs to be expressed in fewer instructions, it was observed that they did not always result in improved performance. For example, on one processor it was discovered that it was possible to improve the performance by NOT using the procedure call instruction but using a sequence of simpler instructions instead. Furthermore, the more complex the instruction set, the greater the overhead of decoding an instruction, both in execution time and silicon area. This is particularly true for processors which used microcode to decode the (macro)instructions.
The term, like its antonym RISC, has become less meaningful with the continued evolution of both CISC and RISC designs and implementations. Modern "CISC" CPUs, such as recent x86 designs like the Pentium 4, whilst they usually support every instruction that their predecessors did, are designed to work most efficiently with a subset of instructions more resembling a typical "RISC" instruction set.
Based on a FOLDOC entry. (1994-10-10)