Like the 68000 before it, the 88000 was considered to be a very "clean" design. It was a pure 32-bit system, using a true Harvard architecture with completely separate data and address busses (and caches), had a small but powerful command set, and—like all Motorola CPUs—did not use memory segmentation.
The first implementation of the 88000 design was in the 88100 CPU, which included an integrated FPU. Mated to this was the 88200 MMU and cache controller. Building a system out of this 1st generation 88000 required both chips and considerable wiring between them, driving up costs. This is likely another major reason for the 88000's limited success.
This was later addressed in the 88110, which combined the two chips into a single package. An additional modification made at the behest of MITs *T project which resulted in the 88110MP, including on-chip communications for use in multi-processor systems.
In the late 1980s several companies were actively watching the 88000 for future use, including NeXT and Apple Computer, but both gave up by the time the 88110 was available in 1990. The only widespread use would be in the Data General AViiON series, but they were one of the only remaining customers in 1995 when they went all-Intel. The only other known use was in the Japanese 4-processor OMRON luna88k machines, which were used for a short time on the Mach kernel project at Carnegie Mellon University.
In the early 1990s Motorola joined the AIM effort to create a new RISC design based on the IBM POWER design. They worked a few features of the 88000 into the new PowerPC design to offer their customer base some sort of upgrade path. At that point the 88000 was dumped as soon as possible.
In keeping with other Motorola CPU designs, the 88000 is also referred to as the m88k