The 68020 had 32-bit internal and external data and address buses and a 256-byte instruction buffer, arranged as 64 direct-mapped 4-byte entries. A lower cost version, the 68EC020, only had a 24-bit address bus.
The 68020 added many improvements to the 68010 including a 32-bit arithmetic and logical unit (ALU) and external data bus and address bus, and new instrucitons and addressing modes. The 68020 (and 68030) had a proper three-stage pipeline.
The new instructions included some minor improvements and extensions to the supervisor state, some support for high-level languages which did not get used much (and was removed from future 680x0 processors), bigger (32 x 32-bit) multiply and divide instructions, and bit field manipulations.
The new adderessing modes added another level of indirection to many of the pre-existing modes, and added quite a bit of flexibility to various indexing modes and operations.
The instruction buffer (an instruction cache) was 256 bytes, arranged as 64 direct-mapped 4-byte entries. Although small, it made a significant difference in the performance of many applications.
The 68881 and the faster 68882 FPU (floating point unit) chips could be used with the 68020.
For more information on the instructions and architecture see Motorola 68000.