Main Page | See live article | Alphabetical index


NMOS logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits.

The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the output and low-voltage rail, while a resistor is placed between the output and the high-voltage rail. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the low-voltage rail and the output. As an example, here is a NOR gate in NMOS logic. Note how the output will be low if either input A or input B is high.

     __|   |__          
    |         |       Rhi
low__| B |___ ___----___high
    |   _|_   |   |   ----
    |__|   |__|   |
pull-down network

While NMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can literally be made with one type of component), it has several shortcomings as well. The worst problem is that a DC current flows through an NMOS gate when the PDN is active, that is whenever the output is low. This leads to static power dissipation even when the circuit sits idle. Also, NMOS circuits are slow to transition from low to high. When transitioning from high to low, the transistors provide low resistance, and the capacitance of the output drains away very quickly. But the resistance between the output and high is much greater, so the high to low transition takes longer. Using a resistor of lower value to speed up the process is a mixed blessing as this does also inflate power dissipation. Additionally, the asymmetric behaviour makes NMOS circuits susceptible to noise.

These disadvantages are why NMOS logic has been supplanted by CMOS both in low-power and in high-speed digital circuits, such as microprocessors, during the 1980s.