ECL gates use differential amplifier configurations at the input stage. A bias configuration supplies a constant voltage at the midrange of the low and high logic levels to the differential amplifier, so that the appropriate logical function of the input voltages will control the amplifier and the base of the output transistor. The propagation time for this arrangement can be less than a nanosecond.
Other noteworthy characteristics of the ECL family include the fact that the large current requirement is approximately constant, and does not depend significantly on the state of the circuit. This means that ECL circuits generate relatively little power noise, unlike many other logic types which typically draw far more current when switching than quiescent, for which power noise can become problematic. ECL circuits operate with negative power supplies, and logic levels incompatible with other families, which means that interoperation between ECL and other designs is difficult. The fact that the high and low logic levels are relatively close mean that ECL suffers from small noise margins, which can be troublesome in some circumstances.
The drawbacks associated with ECL have meant that it has been used mainly when high performance is a vital requirement, and other families (particularly advanced CMOS variants) have been gradually taking over ECL use in some applications. However, some experts predict increasing use of ECL in the future, particularly in conjunction with more widespread adoption of advanced semiconductors such as GaAs.