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Dynamic random access memory

DRAM is a type of random access memory that stores each bit of data in a separate capacitor. The amount of electric charge stored in the capacitor determines whether the bit is considered 1 or 0. As leakage causes the charge on a capacitor to decay, the information gets lost eventually, unless the charge is refreshed periodically. This puts DRAM in the class of volatile memory devices.

Refresh logic is commonly used with DRAMs to automate the periodic refresh. This makes the circuit more complicated, but the drawback is usually outweighed by the fact that capacitors are cheap and small, so high-density, low-power memory chips can be made using this technology. The alternative to DRAM is SRAM.

An important feature of DRAMs is called address multiplexing. This technique splits the address in half and feeds each half in turn to the chip on the same set of pins. Therefore a DRAM needs only half as many address pins as an SRAM of the same capacity, allowing it to be produced in a smaller, cheaper package.

Many microprocessors include control logic for DRAMs, relieving the circuit designer from the need to provide address multiplexing logic.

Table of contents
1 Designing with DRAM
2 Special Types of DRAM

Designing with DRAM

The address multiplexing mentioned above is the key to understanding DRAM. The chip has a large array of memory capacitors that are arranged in rows and columns. To read one location in the array, the control circuit first calculates its row number, which it places on the DRAM's address pins. It then toggles the row address select (RAS) pin, causing the DRAM to read the row address. Internally, the DRAM connects the selected row to a bank of amplifiers called sense amplifiers, which read the contents of all the capacitors in the row. The control circuit then places the column number of the desired location on the same address pins, and toggles the column address select (CAS) pin, causing the DRAM to read the column address. The DRAM uses this to select the output of the sense amplifier corresponding to the selected column. After a delay called the CAS access time, this output is presented to the outside world on the DRAM's data I/O pin.

To write data to the DRAM, the control logic uses the same two-step addressing method, but instead of reading the data from the chip at the end of the operation, it provides data to the chip at the start of the operation.

After a read or write operation, the control circuit returns the RAS and CAS pins to their original states to ready the DRAM for its next operation. The DRAM requires a certain interval called the precharge interval between operations.

Once the control circuit has selected a particular row, it can select several columns in succession by placing different column addresses on the address pins, toggling CAS each time, while the DRAM keeps the same row activated. This is quicker than accessing each location using the full row-column procedure. This method is useful for retrieving microprocessor instructions, which tend to be stored at successive addresses in memory.

The above description is for a one-bit DRAM. Many DRAMs are multibit devices (often four or eight bits), having a number of storage arrays operating simultaneously. Each array is attached to its own data I/O pin, allowing multiple bits of data to be transferred on each read or write. This is logically equivalent to having multiple one-bit DRAMs operating in tandem, but uses less space since all the arrays share the same address and control pins.

Special Types of DRAM

Fast page mode DRAM

Fast page mode DRAM is also called FPM DRAM or Page mode DRAM or Fast page mode memory or Page mode memory. In many applications, data is often transferred to and from DRAM in bursts to consecutive addresses. Fast page mode DRAM simplifies this type of operation by providing an automatic column counter. The controller selects a row (also called a page) and column, as with plain DRAM, and reads or writes the selected location. The DRAM then automatically increments the column address, allowing the controller to access the next location without having to supply a new address. This saves time, and increases the performance of the system when reading or writing bursts of data.

Extended data out (EDO) DRAM

EDO DRAM is similar to Fast Page Mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved speed.

Synchronous Dynamic RAM (SDRAM)

SDRAM is an improved type of DRAM. Whilst DRAM has an asynchronous interface, meaning that it reacts immediately to changes in its control inputs, SDRAM has a synchronous interface, meaning that it waits for a clock pulse before responding to its control inputs. The clock is used to drive an internal finite state machine that can pipeline incoming commands. This allows the chip to have a more complex pattern of operation than plain DRAM.

Pipelining means that the chip can accept a new command before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears a fixed number of clock pulses after the read command. It is not necessary to wait for the data to appear before sending the next command. This delay is called the latency, and is an important parameter to be considered when purchasing SDRAM for your computer.

SDRAM has now (2000s) replaced plain DRAM in modern computers, because of its greater speed.


Rambus DRAM (RDRAM) is internally similar to DDR SDRAM, but uses a special method of signalling developed by the Rambus Company that allows faster clock speeds. RDRAM chips are packaged on modules called RIMMs, which are not compatible with the DIMMs used for plain SDRAM. Intel licensed the Rambus technology and introduced chipsets with Rambus support.

Double data rate (DDR) SDRAM

Double data rate (DDR) SDRAM is a later development of SDRAM. All types of SDRAM use a clock signal that is a square wave. This means that the clock alternates regularly between one voltage (low) and another (high), usually millions of times per second. Plain SDRAM, like most synchronous logic circuits, acts on the low-to-high transition of the clock and ignores the opposite transition. DDR SDRAM acts on both transitions, thereby halving the required clock rate for a given data transfer rate.


VRAM is a dual-ported version of DRAM formerly used in graphics adaptors. It is now amost obsolete, having been superseded by SDRAM and SGRAM. VRAM has two paths (or ports) to its memory array that can be used simultaneously. The first port, the DRAM port, is accessed as with plain DRAM. The second port, the video port, is read-only, and is dedicated to feeding a fast stream of data to the display. To use the video port, the controller first uses the DRAM port to select the row of the memory array that is to be displayed. The VRAM then copies that entire row to an internal shift-register. The controller can then continue to use the DRAM port for drawing objects on the display. Meanwhile, the controller feeds a clock called the shift clock (SCLK) to the VRAM's video port. Each SCLK pulse causes the VRAM to deliver the next item of data, in strict address order, from the shift-register to the video port. For simplicity, the graphics adaptor is usually designed so that the contents of a row, and therefore the contents of the shift-register, corresponds to a complete horizontal line on the display.

Synchronous graphics RAM (SGRAM)

It is a specialised form of SDRAM for graphics adaptors. It adds functions such as bit masking (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour).

Pseudostatic RAM (PSRAM)

It is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to static RAM (SRAM). It combines the high density of DRAM with the ease of use of true SRAM.