Table of contents |

2 Response type 3 Accuracy 4 Sampling rate 5 Aliasing 6 ADC structures 7 See also |

The resolution of the converter indicates the number of discrete values it can produce. It is usually expressed in bits. For example, an ADC that encodes an analog input to one of 256 discrete values has a resolution of eight bits, since

- 2
^{8}= 256.

Most ADCs are linear, which means that they are designed to produce an output value that is a linear function of, i.e. proportional to, the input. Another common type is the logarithmic ADC, which is used in telecommunications systems where the amplitude of the input signal varies over a wide range. The logarithmic ADC compresses the input signal into a smaller number of bits than a linear ADC with the same input range and resolution.

Accuracy depends on the error in the conversion. If the ADC is not broken, this error has two components: quantization error and (assuming the ADC is intended to be linear) non-linearity. These errors are measured in a unit called the *LSB*, which is an abbreviation for *least significant bit*. In the above example of an eight-bit ADC, an error of one LSB is 1/256 of the full signal range, or about 0.4%.

Quantization error is due to the finite resolution of the ADC, and is an unavoidable imperfection in all types of ADC. The magnitude of the quantization error at the sampling instant is between zero and half of one LSB.

All ADCs suffer from non-linearity errors caused by their physical imperfections, causing their output to deviate from a linear function (or some other function, in the case of a deliberately non-linear ADC) of their input. These errors can sometimes be mitigated by calibration, or prevented by testing.

Commonly, the analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called sampling rate of the converter.

The key idea here is that a continuously varying bandlimited signal can be sampled( ie. the signal values at intervals of time T, the sampling time, are measured and stored.) and then the original signal can be EXACTLY reproduced from the discrete-time values by an interpolation formula. The accuracy is however limited by quantization error. However this faithful reproduction is only possible if the sampling rate is higher than twice the highest frequency component present in the signal. This is essentially what is called Shannon's sampling theorem.

If the digital values produced by the ADC are, at some later stage in the system, converted back to analog values by a digital to analog converter or DAC, it is desirable that the output of the DAC is a faithful representation of the original signal. If the input signal is changing much faster than the sample rate, then this will not be the case, and spurious signals called *aliases* will be produced at the output of the DAC. This problem is called *aliasing*.

To avoid aliasing, the input to an ADC is often filtered to prevent it from changing faster than the sample rate. This filter is called an *anti-aliasing* filter.

There are four common ways of implementing an electronic ADC:

- A
**direct conversion ADC**or**flash ADC**has a comparator that fires for each decoded voltage range. The comparator bank feeds a logic circuit that generates a code for each voltage range. Direct conversion is very fast, but usually has 8 bits of resolution (256 comparators) or less. - A
**successive-approximation ADC**uses a comparator to reject ranges of voltages, eventually settling on a final voltage range. For example, the first comparison might decide the most significant bit of the output, the next comparison decides the next-most significant bit, etc. These convert very fast, and have good resolutions and quite wide ranges. They are more complex than other designs. - A
**delta-encoded ADC**has an up-down counter that feeds a digital-to-analog converter DAC. The input signal and the DAC both go to a comparator. The comparator controls the counter. The circuit uses negative feedback from the comparator to adjust the counter until the DAC's output is close enough to the input signal. The number is read from the counter. Delta converters have very wide ranges, and high resolution, but the conversion time is not predictable when there are fast changes in the input. Delta converters are often very good choices to read real-world signals. Most signals from physical systems do not change abruptly. Some converters combine the delta and successive approximation approaches; this works especially well when high frequencies are known to be small in magnitude. - A
**ramp-compare ADC**produces a saw-tooth signal that ramps up, then quickly falls to zero. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, and the timer's value is recorded. Timed ramp converters require the least number of transistors. The ramp time is sensitive to temperature because the circuit generating the ramp is often just some simple oscillator. There are two solutions: use a clocked counter driving a DAC and then use the comparator to preserve the counter's value, or calibrate the timed ramp. A special advantage of the ramp-compare system is that comparing a second signal just requires another comparator, and another register to store the voltage value.

These are usually integrated circuits.

Most converters sample with 6 to 24 bits of resolution, and produce fewer than 1 megasample per second. Mega and gigasample converters are available, though (Feb 2002); megasample converters are required for digital video editing. Commercial converters usually have ±0.5 to ±1.5 LSB error in their output.

The most expensive part of an integrated circuit is the pins, because that makes the package larger, and each pin has to be connected to the integrated circuit's silicon. To save pins, it's common for ADCs to send their data one bit at a time over a serial interface to the computer, with the next bit coming out when a clock signal changes state, say from zero to 5V. This saves quite a few pins on the ADC package, and in many cases, does not make the overall design any more complex. (A notable exception is in connecting the converters to microprocessors which use memory-mapped IO.)

Commercial ADCs often have several inputs that feed the same converter, usually through an analog multiplexer. Different models of ADC may include sample-and-hold circuits, instrumentation amplifiers or differential inputs, where the quantity measured is the difference between two voltages.